Advances in semiconductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or complete systems on individual integrated circuits. Additionally, as the density of integrated circuits has grown, the power requirements for computing systems (from embedded systems to servers) have also escalated. Furthermore, software inefficiencies, and its requirements of hardware, have also caused an increase in computing device energy consumption. In fact, some studies indicate that computing devices consume a sizeable percentage of the entire electricity supply for a country, such as the United States of America. As a result, there is a vital need for energy efficiency and conservation associated with integrated circuits. These needs will increase as servers, desktop computers, notebooks, ultrabooks, tablets, mobile phones, processors, embedded systems, etc. become even more prevalent (from inclusion in the typical computer, automobiles, and televisions to biotechnology).
As general background, processors include a variety of logic circuits fabricated on a semiconductor integrated circuit (IC). These logic circuits are collectively targeted to perform at a specific power envelope referred to as the “Thermal Design Power” (TDP). “TDP” identifies the maximum amount of power that an electronic device implemented with the processor is required to dissipate. For example, a cooling system in a computer may be designed for a 35 watt TDP, which means that it will need to dissipate heat for up to 35 watts of power usage in order to avoid exceeding the maximum junction temperature for the processor.
Besides power, different processors are targeted to perform at different frequencies depending on which stock-keeping unit “SKU” (or bin) that processor is assigned. In other words, processors are assigned to different SKUs (or bins) based on their particular TDP frequency, namely the guaranteed frequency at which the processor will run, under normal operating conditions, within the TDP constraints.
Normally, the TDP frequency is set to an operating frequency that can be maintained by the processor even when operating under its worst case conditions from a power usage perspective. One worst case condition may involve a condition where all of the processor cores are active and operating at the TDP app ratio. The “TDP app ratio” is the highest power level in real world applications.
Over time, processors have been designed to support a secondary operating mode, herein referred to as “Turbo” mode. “Turbo” mode was created because a processor rarely operates in its worst case conditions, and thus, there is normally headroom for that processor to operate at a performance level higher than the TDP frequency and still remain within established power limits.
Currently, the most common mechanisms for ensuring that power limits are not exceeded are (1) power budget management (PBM) and (2) internal power meters. PBM is a mechanism that limits the exponential running average power consumption to some programmable value over a programmable time window. As shown in equation (1), PBM performs a power evaluation for an interval (τ) by determining how much power is gained or lost relative to a power budget for this interval and then exponentially smoothing this result based on a previous interval evaluation. Using this computed budget, the processor is able to decide what P-state can be used while staying within the power budget as set forth below in equation (1). The “P-state” is a frequency and voltage operating point that is scalable so that frequency can be adjusted to increase performance at the expense of higher power or frequency can be decreased to realize power savings.Budget=τ·(previous budget)+(power−TDP)·Δτ  (1)
A “power meter” is a processor-internal mechanism that estimates power consumption, which may be determined from leakage power and active power. Leakage power is estimated based on a reference leakage value multiplied by a function of voltage and temperature known by the processor while active power is determined as follows:Active power=CV2f, where  (2)
“C” is the estimated capacitance,
“V” is the controlled voltage, and
“f” is the controlled frequency.
While the above-described mechanisms are useful for increasing processor performance (e.g. operating frequency), they do not adequately, for power conservation, constrain frequency variations between processors having the same architecture and assigned to the same SKU (or bin). Although some processors may have the same general architecture as others, they will vary widely in power consumption and operation, even within the same SKU. One reason is that actual power consumption may vary greatly due to differences in voltage vs. frequency characteristics, dynamic capacitances (Cdyns), leakage power, operating temperatures, etc. Since the power meter takes all of this per part information into account, the estimated power will also vary and result in performance disparities between processors, even ones in the same SKU, when such information is used by PBM for turbo frequency decisions.
Performance disparity between processors within the same SKU (or bin) is problematic from a business perspective, as it can lead to performance disparities in the end products (electronic devices), which may adversely effect the customer's overall impression of that product. In order to avoid bin inversions (e.g., all processors in bin X should perform as well or better than all processors in bin X−1) and support only slight variations in operating frequency for processors within the same bin, a power meter would need to be configured to report the same energy across all parts in a bin or adjust the power limits such that all parts will get the same performance despite different power levels. Retrofitting this uniformity onto something which is inherently different per part is extremely difficult given the large number of variables—workload, temperature, part characteristics, etc.